Show simple item record

dc.contributor.advisorAgrawal, Vishwani
dc.contributor.authorTaher, Farah
dc.date.accessioned2013-07-10T21:38:52Z
dc.date.available2013-07-10T21:38:52Z
dc.date.issued2013-07-10
dc.identifier.urihttp://hdl.handle.net/10415/3714
dc.description.abstractAt present, performance and efficiency of a system-on-chip (SoC) design depends significantly on the on-chip global communication across various modules on the chip. On-chip communication is mostly implemented using a bus architecture that runs long distances, covering significant area of the integrated circuit. Difficult challenges in designing of a large SoC, e.g., one containing many processor cores, include hardware area, power dissipation, routing complexity, congestion and latency of the communication network. In this work, we propose an analog bus for digital data. In our scheme we replace n wires of an n-bit digital bus carrying data between cores with just one (or few) wire(s) carrying analog signal(s) encoding 2^n levels of voltage. This analog bus uses digital-to-analog converter (DAC) drivers and analog-to-digital converter (ADC) receivers. Such on-chip communication scheme can potentially save hardware area and power. Reduction in number of wires saves chip area and the reduction in total intrinsic wire capacitance consequently reduces bus power consumption. The scheme should also reduce signal interference and crosstalk by eliminating the need for multiple line drivers and buffers. In spite of overheads of the DACs and ADCs, savings in power consumption from our scheme is significant. We have carried out simulated experiments that serve as a proof-of-concept by evaluating power consumption of a single wire with DAC/ADC encoding in comparison to an n-bit digital bus of a large system. SPICE simulation for an ideal case shows that the ratio of bus power consumed by the proposed analog scheme to a typical digital scheme (without bus encoding or differential signaling) is given by P(analog)/P(digital) = 1/(3n). For 500MHz frequency and 1mm intermediate wire line, 4-bit replacement analog bus consumes 16µW over 219µW in parallel bus. Whereas, the 8-bit replacement bus consumes 18µW over the 470µW power consumption in the 8-bit parallel bus.en_US
dc.rightsEMBARGO_NOT_AUBURNen_US
dc.subjectElectrical Engineeringen_US
dc.titleA Low-Power Analog Bus for On-Chip Digital Communicationen_US
dc.typethesisen_US
dc.embargo.lengthMONTHS_WITHHELD:6en_US
dc.embargo.statusEMBARGOEDen_US
dc.embargo.enddate2014-01-10en_US


Files in this item

Show simple item record