|dc.description.abstract||The electronics may experience high strain rates under single, sequential and simultaneous exposure to thermo-mechanical and transient dynamics loads at various stages of their life-cycle i.e. manufacturing, transportation, and deployment in field. Models for high-g electronic survivability require high strain rate properties of materials for different loading scenarios. Second-level interconnects have high susceptibility to failure in fine pitch electronics. In the recent past, the electronics industry has migrated to lead-free solder alloy compositions or so called “green” products under the ROHS initiative. Tin-Silver-Copper (SnAgCu or SAC) alloys are being widely used as replacements for the standard 63Sn-37Pb eutectic solder. High strain rate properties of electronic materials are scarce.
In this research work, a new test-technique developed by the author has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 sec-1. The high strain rate properties of Sn1Ag0.5Cu and Sn3Ag0.5Cu lead-free solder alloys under prolonged exposure to high temperature have been measured. An impact hammer has been used in conjunction with digital image correlation and high-speed video for measurement of material constitutive behavior of lead-free SAC alloys in the strain rate range of 1-100sec-1. Thin-bar samples have been fabricated by reflowing solder in glass tubes using reflow profiles typical of lead-free assemblies. Bar sample thickness has been selected to be in the neighborhood of typical heights of solder interconnects in fine-pitch electronics. Sn1Ag0.5Cu and Sn3Ag0.5Cu specimen have been subjected to various lengths of aging temperatures, aging times (0-2 months) and strain rates. Rate independent material AL7075-T6 has been used as a bench mark experiments at various strain rates in the range of 1-100 sec-1. The experimental data has been fit to the Ramberg Osgood model and implemented in the finite element analysis for full-field strain correlation between DIC and simulation.
Also when electronics are subjected to high strain rates during accidental drop and shock there are high possibility of second level solder interconnects to fracture completely due to dynamic crack propagation. Additional failure modes may include copper trace fracture, underfill cracking, chip delamination and chip cracks. Previously, modeling approaches are based on the classic continuum theory of solid mechanics which uses partial differential equations (PDE). Since, PDE are not valid in presence of discontinuities such as cracks, voids, any numerical scheme derived from these equations fails to model cracks. Henceforth, such methods require auxiliary equations that govern the damage initiation and damage progression. These auxiliary equations get more complicated to solve discontinuities which can occur simultaneous at multiple locations in 3D fashion. In order to overcome these modeling issues an alternative theory know as peridynamic theory which uses integral equations has been implemented in this work. Peridynamic scheme reformulates the basic mathematical description of solid mechanics in order to retain the same equation on or off the discontinuity location. Previosuly, feasibility of using peridynamics in drop simulation of electronics has been demonstrated using EMU code. Use of finite element based peridynamics for electronics packaging under drop and shock in this work is new.||en_US