DVF4: A Dual Vth Feedback Type 4-Transistor Level Converter
Type of Degreethesis
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Power dissipation in digital circuits has become one of the primary concerns in elec- tronic design. With the increasing usage of portable devices, there are severe restrictions being placed on the size, weight and power of batteries. Circuits consuming more power require batteries to be charged more frequently. It has therefore become important not only to optimize circuits for delay and area, but also for power. This has led to a growing interest in fi nding newer and more eff ective power reduction techniques. Power reduction techniques at various levels of abstraction have been used in modern digital world. The popular techniques include multiple supply voltages, multiple threshold voltages, clock gating, architecture tech- niques. In this work we propose a level converter for dual supply voltages in digital designs in order to get a reduction in power consumption. This level converter can be used in circuit using multi supply voltages system where low supply gates are feeding high supply gates. The proposed level converter is compared with the existing level converter for power consumption and delay. The level converter is individually optimized for each supply voltage for low power consumption and then used with various simulation setups to indicate the advantage of using the proposed level converter. The saving on power consumption is upto 76% and the delay savings is upto 52% better than the existing level converters.