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Finding Optimum Clock Frequencies for Aperiodic Test
Date
2014-04-29Author
Gunasekar, Sindhu
Type of Degree
thesisDepartment
Electrical EngineeringMetadata
Show full item recordAbstract
With scale down in technology, size and complexity of integrated circuits increase. The
scan method is the most popular technique of testing sequential circuits today. In this
method,
ip-
ops functionally form one or more shift registers in the test mode. Faults
in the combinational logic can be tested by shifting test patterns in and out of the shift
register. Larger circuits these days consist of many
ip-
ops and the scan design has large
shift registers, which require many clock cycles for loading and unloading. An ATE is
used to test these scan circuits for faults after fabrication. The testing cost of using an
ATE increases directly with the time spent in testing the chip and adds to the nal cost
of the chip. In general, power constraints do not allow speeding up of the clock during
test. For the complex integrated circuits today, long test times are a concern. A recently
proposed methodology [37] reduces the test time on ATE using an aperiodic clock with many
di erent frequencies. In practice, the ATE generates only a limited number of frequencies
and determining an optimum set of frequencies is a discrete optimization problem. This work
discusses an algorithm to obtain the optimum set of frequencies for test time reduction. The
algorithm is implemented by simulating ISCAS '89 benchmark circuits and veri ed on the
Advantest T2000GS ATE located at Auburn University, Alabama. It is observed that by
using just four optimum frequencies, that the tester allows, test time reductions of up to
52% can be obtained in some benchmark circuits.
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