Layout and Assembly of a High Efficiency Multi-Phase Buck Converter Utilizing Chip Scale GaN Devices

Abstract

As the world becomes increasingly immersed in the Information Age, more and more supercomputers and datacenters must be built to keep up with humanity’s demand for electronic information. As the number of these facilities and their physical size continue to grow, so do the power demands that they place on their local power grids. Much of this demand is a direct result of the processing hardware being utilized, but a large majority of this is wasted power, lost within the system due to various areas of inefficiency. This work will describe the implementation of a prototype design for a Point of Load voltage regulator for use in power datacenter processors using new technology GaN FETs to generate efficiencies greater than 90%. This work will detail a process used to prototype with these chip scale package GaN devices, allowing for a faster development cycle of a converter design within organizations that may not have access to advanced assembly equipment. This process details how to assemble these GaN devices in a manner that provides very high yields, while considering the possible equipment limitations of most organizations. This process is then used in the implementation of these GaN devices in the creation of a Point of Load prototype to demonstrate the improved efficiencies possible by using these GaN devices. Design, layout, assembly, and testing stages are discussed for two versions of the prototype, detailing many of the decisions made during the design process to fully utilize these iii devices. This work provides information useful to any organization considering using these new generation GaN devices in future designs by demonstrating their capabilities, discussing the features of the technology, reviewing some guidelines that may be beneficial during the design stages, and by providing a high yield assembly method that can be implemented within most well equipped organizations.