Characterization of Die Stress in Microprocessor Packaging Due to Mechanical, Thermal, and Power Loading
Roberts, Jordan C.
Type of Degreedissertation
MetadataShow full item record
Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of mechanical loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k dielectric top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. (111) silicon test chips were used to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chip die are subjected to relatively large compressive in-plane normal stresses after solder reflow. It was also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general "rule of thumb," approximately two-thirds (~66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components during thermal and power cycling without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to slow (quasi-static) temperature changes from 0 to 100 _C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 _C (40 minute cycle, 10 minute ramps and dwells) for up to 9000 cycles. After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach was used to predict the build-up of compressive stress. The method used incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes.