An Efficient Transition Detector Exploiting Charge Sharing
Type of Degreethesis
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Transition detectors have been widely employed for online error and metastability detection, including in Better-Than-Worst-Case (BTWC) timing design of microprocessors that are designed to allow occasional timing errors. Early error detector designs such as Razor introduced a shadow latch with a delayed clock in parallel to the datapath flip-flop for timing-error detection through duplication and comparison. Intel and ARM have presented transition detectors in prototype implementations of BTWC designs that both detect timing errors, and also address the issue of flip-flop metastability. While these designs represent the state-of-art in transition detector design the high area overhead remains a major concern since the circuits may need to be incorporated in almost all the flip-flops in a large design. In this thesis, we propose a much more efficient transition detector exploiting charge sharing (TDCS) that displays ultra-low area overhead. Our design employs a novel combination of short circuit effects and charge sharing based discharge for operation, and reduces by more than half the complexity of conventional transition detector designs. Although the motivation for the TDCS design originates from BTWC design, it can be utilized in various other applications. A TDCS circuit is designed in 45nm technology for evaluation, and analyzed based on a high performance version of the PTM model. Simulation of our TDCS design shows that it can reliably achieve the same functionality as published designs with 60% fewer transistors. Furthermore, corner analysis shows that TDCS is also robust under extreme PVT variations.