Practically Realizing Random Access Scan
Type of DegreeThesis
Electrical and Computer Engineering
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The number of clock cycles in a serial scan (SS) test is often prohibitive as the number of flip-flops (FF) increases. Besides, scan-in and scan-out sequences result in unwanted circuit activity. This increases the test power enormously. The scan process activates all flip-flops in the scan chain, although very few flip-flops need to be set for a targeted fault and only a subset of all the flip-flops needs to be observed. A technique known as Random Access Scan (RAS) can solve these problems. Here every flip-flop is addressed uniquely. In RAS, only the required number of flip-flops is set or reset for a given test and this reduces the set up time of flip-flops significantly. Due to the flexibility of setting the required flip-flops randomly, the test power drastically reduces to a bare minimum. Thus two complementary problems are addressed using the single technique of RAS. These advantages come at a cost of increased area overhead and that is often unacceptable. In this work, we have addressed the problem in such a way that the implementation is practical and the additional area overhead is justified. We have developed a new RAS cell, which minimizes the number of signals otherwise routed to it compared to earlier designs. This improvement saves silicon area. Another contribution of this work is a new RAS cell without a scan-in signal and an added toggle feature. This flip-flop toggles its state when addressed and hence any desired state can be achieved by just addressing it if the current state is known. The scan out structure is also designed in such a way that when a flip-flop is addressed or toggled, the existing value of the flip-flop is read out. This is done using a hierarchical bus structure that drives the data from the addressed flip-flops to a primary output. Considering the limited drive capability of the flip-flops, the hierarchical bus restricts the load that the addressed flip-flop must drive. The flip-flops are addressed using a grid structure controlled by row and column decoders. We evaluated different decoding schemes and concluded that the grid scheme requires the least routing overhead. The intersection of selected row and column addresses lines sets a flip-flop in the scan mode of operation. The address inputs to the decoders are provided from primary input pins. Using this design we have shown that the test cycles can be reduced by 60% compared to a single chain serial scan and the test power saving can be as high as 99% compared to the serial scan. We also provide an algorithm to further decrease the test cycles.