Fabrication and characterization of compliant off-chip double helix and carbon nanotube interconnect

Abstract

Microelectromechanical systems (MEMS) type double helix chip-level electrical interconnect structures are fabricated and characterized in this work. Due to their springlike structure, double helix interconnects have the potential to provide mechanical compliance to compensate for nonidealities, such as nonplanarity and thermal expansion mismatch between chips and substrates. A double helix configuration provides for structures with a high volumetric density of conductor for enhanced current carrying capability and lower electrical resistance. The fabrication process is compatible with wafer-level fabrication and packaging. Instead of using soldered interconnections, the double helix interconnects use pressure to make electrical connection and provide sufficiently low resistance, which is estimated to be approximately 35 ± 15 mΩ in this work. Large arrays of double helix structures have been fabricated and characterized with high yield. The mechanical and electrical models of the structures are presented. Reworkability tests were performed and the structures show a consistent resistance over 50 remating cycles. To characterize the high frequency performance, the double helix were designed and fabricated on top of coplanar waveguides (CPW) as flip-chip interconnects. The structure was characterized and simulated in High Frequency Structural Simulator (HFSS) up to 50 GHz. The measured insertion and reflection loss were less than -0.6 dB and -15 dB, respectively. Other than using a structurally compliant interconnect, one can also use flexible material to gain compliance. A reliable solution-based process to fabricate thick carbon nanotube (CNT) bumps has been developed and is presented in this paper. In contrast to other work of this nature, the process we have developed is capable of fabricating thick and densely packed CNT structures at room temperature with relatively high resolution and controllable film thickness or bump height. CNT structures fabricated using the developed method may find use in sensors or electrical interconnect applications. Raman spectroscopy was used to characterize the fabricated CNT bumps, verifying the CNTs are negligibly affected by the fabrication process. To study the potential application of these CNT bumps for flip-chip interconnections, we examined the deformation of the CNT bumps after flip-chip bonding and performed electrical characterization. The CNT bump interconnects display linear I-V curve with an average resistance of approximately 484 mΩ for a bump with 200 μm diameter and height of 12 μm. The solution deposited CNT interconnects have similar resistance to transferred CNT bumps grown by chemical vapor deposition. Temperature dependent measurements indicate that fluctuation-induced tunneling (FIT) is the most likely electrical conduction mechanism in the CNT bumps. The high frequency performance of the CNT bumps was also simulated in HFSS and characterized. The CNT bumps were deposited as flip chip interconnects on top of a CPW. The performance of the bumps were compared to similarly-sized gold interconnects. High frequency characterization was carried out up to 40 GHz. The return loss is below -15 dB and the insertion loss of the CNT interconnect is 0.3 dB higher than conventional gold bump interconnects per transition. Considering the negligible skin effect of CNT, they have the potential to out-perform conventional metal interconnects at higher frequency.