|Through silicon via (TSV) based three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration,reduced delay and power dissipation, compact device dimension, etc. However, to commercialize 3D IC products, still, many challenges exist. In this dissertation, we focus on conquering two of these challenges. The ﬁrst challenge is to reduce pre-bond faulty TSV diagnosis time. The second challenge is to improve the compound yield and reduce cost of
wafer-on-wafer stacked 3D ICs. Novel ideas are proposed and are demonstrated to be good solutions for these two challenges. Pre-bond TSV testing and defect identiﬁcation is extremely important for yield assurance of 3D stacked devices. In this dissertation, we proposed a three-step optimization method named “SOS3” to greatly reduce pre-bond TSV test time without losing the capability of identifying certain number of faulty TSVs. The three steps of optimization are as follows. First, an ILP (integer linear programming) model is proposed to generate near-optimal set of test sessions for pre-bond TSV diagnosis. The sessions generated by our ILP model identify defective TSVs in a TSV network with the same capability as that of other available heuristic methods, but with consistently reduced test time. Second, an iterative greedy procedure to sort the order of test sessions is proposed. Third, a fast TSV identiﬁcation algorithm is proposed to actually diagnoses the faulty TSVs based on given test sessions.
Extensive experiments are done for various TSV networks and the results show SOS3 as a framework greatly speeds up the pre-bond TSV test. SOS3 provides useful known-good-die
information for 3D die-on-die, die-on-wafer, and wafer-on-wafer stacking.
Wafer-on-wafer stacking oﬀers practical advantages over die-on-die and die-on-wafer
stacking in 3D IC fabrication, but it suﬀers from low compound yield. To improve the yield, a novel manipulation scheme of wafer named n-sector symmetry and cut (SSCn) is
also proposed in this dissertation. In this method, wafers with rotational symmetry are cut
into n identical sectors, where n is a suitably chosen integer. The sectors are then used to
replenish repositories. The SSCn method is combined with best-pair matching algorithm
for compound yield evaluation. Simulation of wafers with nine diﬀerent defect distributions
shows that previously known plain rotation of wafers oﬀers only a trivial beneﬁts in yield. A
cut number four is optimal for most of the defect models. The SSC4 provides signiﬁcantly
higher yield and the advantage becomes more obvious with increase of the repository size
and the number of stacked layers. Cost model of SSCn is analyzed and the cost-eﬀectiveness
of SSC4 is established. Observations made are: 1) Cost beneﬁts of SSC4 become larger
as the manufacturing overhead of SSC4 become smaller, 2) cost improvement of SSC4 over
conventional basic method increases as the number of stacked layers increases and 3) for
most defect models, SSC4 largely reduces the cost even when manufacturing overhead of
SSC4 is considered to be very large.