The Effects of Mechanical Stress on Semiconductor Devices
Type of DegreeDissertation
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Mechanical strains and stresses are developed during the fabrication, assembly and packaging of the integrated circuit (IC) chips. Sources include processes such as shallow trench isolation, wafer backgrinding and dicing, TSV formation, die attachment, and first level packaging (e.g. encapsulation). These stresses and strains cause parametric shifts in the electronic components which change their electrical performance, and can result in devices operating out of specification. The influence of mechanical stress on devices that operate using conduction of majority carriers is often modeled using piezoresistive theory. Extensive investigation has been done on mechanical stress effects on resistors fabricated on integrated circuit chips. In addition, test chips using resistor sensors have been successful in measuring die stresses for various packaging architectures. Stress effects on diodes, field effect transistors (FETs), van der Pauw structures, and CMOS sensor arrays have also been well characterized. The influences of mechanical stress/strain on bipolar junction transistors (BJT) are more complicated than those for other devices. This is because bipolar transistors feature conduction in both n-type and p-type regions, as well as conduction of minority carriers. In prior studies, the influence of stress on BJT behavior has been described using the so-called piezojunction effect, which includes variations in the minority carrier mobility and the intrinsic carrier concentration. Whereas the piezoresistive effect describes the variation of the resistivity components of the majority carriers with applied mechanical stress, the piezojunction effect governs the dependence of the minority carrier conduction on stress. In BJTs, both bandgap and the attendant mobility variations influence various parameters including saturation current IS, collector current IC, base current IB, and DC current gain β. Analog circuits containing bipolar transistors are also affected by stress, including precision voltage references, op-amps, A/D and D/A converters, etc. Experimental data for resistors and resistive channels of CMOS devices have demonstrated that their changes in their electrical characteristics can be explained by linear piezoresistive theory that includes only first order terms. However, most data for bipolar transistors in the literature illustrate non-linear variations of saturation current, collector current, and base current with applied uniaxial stress. In this dissertation, mechanical stress related phenomena for several electronic devices including resistors, field effect transistors, and bipolar transistors have been explored. In the first portion of this work, measurement and other errors have been investigated for multi-element resistor sensor rosettes on (111) silicon. Resistors are widely used in the semiconductor industry as silicon stress sensors. They are fabricated on the surface of test chips and then used to extract stresses over the die surface. To make such measurements, the user must measure the changes in the resistances of the sensors, the piezoresistance coefficient values, and the temperature. These experimental measurements inherently contain certain uncertainties in their values. In this work, an error analysis was performed, which included uncertainties in measurements and calibration constants. This sensitivity analysis included direct calculations of the sensitivities of the extracted stresses to uncertainties in the calibrated piezoresistive coefficients, measured sensor resistances, and the measured temperature. In the second portion of this work, calibration of field effect transistor (FET) stress sensors was investigated. Stress effects on FETs can be modeled using piezorsistive theory similar to resistors. In this dissertation, the dependence of the piezoresistive coefficients on the drain current operating point of the FET device has been explored. Both the PMOS and NMOS devices demonstrated strong drain current dependencies. The piezoresistance coefficients were also expressed as a function of carrier mobility in the channel region. In the third and final portion of this work, stress effects on bipolar junction transistors have been investigated. The primary goal of this research topic was to understand and model the impact of mechanical stress on bipolar transistors and precision analog circuits. Although piezojunction coefficients have previously been proposed in the literature to describe the variation of transistor saturation currents under stress, there has not been a comprehensive modeling effort for use in circuit simulation. In this dissertation, a basic charge-control model for the transistor has been proposed that adequately captures the macroscopic impact of stresses on the BJT device characteristics. In addition, the developed approach has been used to model the influence of stress on analog circuits employing these devices. This work has provided an understanding of the dominant effects of stress on the basic BJT model parameters. To support the proposed models, the response of BJTs to the controlled application of mechanical stress has been characterized experimentally. Test structures have been utilized to characterize the stress sensitivity of vertical bipolar devices fabricated on both (100) and (111) silicon wafers. Uniaxial normal stresses were applied using a four-point-bending fixture, and changes in the electrical performance of the BJTs were observed. The experimental data acted as a benchmark in the development of the theoretical model, and the developed stress equations for the BJT have been shown to have excellent correlations with the experimental results. Based upon the current gain and saturation current data, a methodology has been developed for properly separating the contributions of intrinsic carrier concentration and minority carrier mobility on the overall stress induced variations of the collector current and current gain of the BJT. In the future, the developed formulations can be applied to theoretically optimize transistor design, placement, orientation, and processing to minimize the impact of fabrication and packaging induced die stresses.