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dc.contributor.advisorNelson, Victoren_US
dc.contributor.authorZeng, Kunpengen_US
dc.date.accessioned2015-07-21T21:34:37Z
dc.date.available2015-07-21T21:34:37Z
dc.date.issued2015-07-21
dc.identifier.urihttp://hdl.handle.net/10415/4702
dc.description.abstractWith the increase of integration density at chip level, the controllability and observability of defects become complicated, resulting in limited physical probe access to I/O pins. It is impractical to apply test stimulus to all the input pins and capture outputs from output pins on a chip within a printed circuit board (PCB). Boundary scan is a helpful method to test with reduced physical probe access to IC pins on complex PCBs. JTAG is mostly synonymous with the term ``Boundary scan". By adding some JTAG test logic, including four JTAG pins (TCK, TMS, TDI and TDO), several registers, and a TAP controller, we are able to program the ADVANTEST T2000GS tester to perform functional test of an IC with physical access limited to only JTAG pins. In addition, some other JTAG functions, such as checking the device type and the integrity of JTAG pins, examine the correctness of on-chip logic etc. can also achieved by JTAG. The proposed procedure for performing functional test using JTAG pins was verified through experiments. The experiments are carried on the Advantest T2000GS ATE located at Auburn University. The device under test (DUT) is a Mercury development board, which contains a XILINX Spartan-3A FPGA. Benchmark circuits of ISCAS'85 and ISCAS'89 are used as the configured on-chip logic. In addition, the verification of FPGA JTAG interface and components are also conducted.en_US
dc.subjectElectrical Engineeringen_US
dc.titleExploiting Boundary Scan functions of FPGA on ATEen_US
dc.typeMaster's Thesisen_US
dc.embargo.statusNOT_EMBARGOEDen_US
dc.contributor.committeeAgrawal, Vishwanien_US
dc.contributor.committeeSingh, Aditen_US


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