Diagnostic Test Generation for Path Delay Faults in a Scan Circuit
Type of DegreeMaster's Thesis
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With the increase of density, speed and test time of large VLSI circuits, man- ufacturers are eager to nd e cient ways to bring up yields. Often, VLSI testing only tells if a circuit is faulty but is unable to locate faults. Diagnosis helps nd locations of faults so that problems with the design and manufacturing process can be analyzed. By adding a few logic gates and only two ip- ops to the netlist model, we are able to generate distinguishing tests for path delay faults with the same tools as are used for detecting a stuck-at fault. As a result, the capability of automatic test pattern generation (ATPG) tool is improved for diagnosis of path delay faults. Our proposed diagnosis method improves the capability to pinpoint the cause of failure by narrowing down the list of suspected fault candidates. The proposed ATPG procedure generates tests to distinguish between path delay fault pairs, i.e., two faults are required to have di erent output responses. Test pattern generated from the model is shown to distinguish between any pair of path delay faults. In order to evaluate the improvement in tests we use a previously proposed Diagnostic Coverage (DC) metric. We apply our diagnosis method to several ISCAS'89 benchmark circuits. Experi- mental results show the improvement of DC. The proposed diagnosis system may also be used for other fault models if behavior of faults can be mapped onto a stuck-at fault. It may also enhance the ability of conventional ATPG tools to signi cantly improve DC without increasing their complexity.