|dc.description.abstract||Determining the location and cause of a defect in a faulty circuit plays a vital role in VLSI testing. These are critical factors in boosting product quality and reducing manufacturing costs.
An automatic test generation system is presented which combines detection test and diagnostic test. It generates a diagnostic test for a modeled transition fault pair by making a simple modification of netlist. Using a conventional ATPG, a test can be generated for a specific stuck-at fault in the netlist model. The test is an exclusive test for the pair of transition delay faults. If an exclusive test exists, the fault pair can be distinguished in original full-scan circuit. This is followed by diagnostic fault simulation to identify undistinguished fault pairs and to update the diagnostic coverage (DC), which is a measure of the capability tests to diagnose faults. A 100\% DC means that each fault can be distinguished from all other faults. The exclusive test generation continues until an adequate goal for DC is achieved.
This thesis presents a two-timeframe ATPG model for a full-scan sequential circuit.It inserts a few logic gates to the original circuit netlist for analysis purpose only, then expands to a purely two-timeframe combinational logic ATPG model.
We have enhanced the ability of automatic test generation system to distinguish transition delay fault pairs. Thus, a transition delay fault pair can be either distinguished or proved equivalent, i.e., two faults have the exact same output responses at all nodes.
Compared to sequential logic, combinational logic is more effective for redundant fault identification. This property is exploited in our exclusive test generation system. The entire system was implemented using Python programming language and commercially available CAD programs. The proposed method is practical as the modeling, relatively simple and with improved DC. This is observed from experimental results on ISCAS'89 sequential benchmark circuits.||en_US