This Is AuburnElectronic Theses and Dissertations

Thin Film Multichip Packaging for High Temperature Geothermal Application




Fang, Kun

Type of Degree



Electrical Engineering


A DOE sponsored study by MIT concluded that geothermal energy could provide 100,000 MWe or more in 50 years by using advanced technology knowns as Enhanced Geothermal Systems (EGS). In EGS, the measurement-while-drilling (MWD) tool is a crucial part. The MIT study indicates that high temperature instrumentation for geothermal is a key technology deficiency. In-well EGS electronics must operate at temperatures of >250C and production monitoring electronics must operate for 10-20 years. In this work, a multilayer thin film substrate technology with flip chip bonding has been developed to interconnect multiple SiC devices along with passive components. Key elements of this high temperature multichip packaging technology include the thin film multilayer interconnection substrate and die assembly with flip chip bonding. New developments in each of these areas for high temperature operation have been discussed in this research. The multilayer substrate technology based on AlN substrate, thin film metals and insulator has been developed for packaging of digital SiC electronics. The target operating temperature is 300C with potential for higher temperature use. The conductor was vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride was used for the interlayer dielectric. The effect of 300C storage on the multilayer structure has been studied. In addition, the electrical properties of the dielectric, including leakage current, capacitance and dissipation factor, have also been measured as a functional of aging temperature and aging time. The leakage current at 300C with constant 20V bias has also been investigated. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Shear test has been performed on flip chip samples after thermal aging test, thermal cycling test and thermal aging test with shock and vibration. Besides single stud-bump configuration, a double bump configuration has also been developed and evaluated to improve the thermal cycling performance of stud bump assembly. With thin film multichip packaging technology developed in this project, five kinds of digital circuit boards were fabricated at Auburn University and tested at GE Global Research Center. The reliability of these digital circuit boards based on electrical performance after thermal aging test, vibration test and shock test has been discussed.