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dc.contributor.advisorSingh, Aditen_US
dc.contributor.authorHan, Chaoen_US
dc.date.accessioned2015-07-29T14:18:37Z
dc.date.available2015-07-29T14:18:37Z
dc.date.issued2015-07-29
dc.identifier.urihttp://hdl.handle.net/10415/4801
dc.description.abstractCMOS open defects are breaks in wires or defective transistors within some library cell causing pull up or pull down failure of the defective gates. Traditionally, TSOF (transistor stuck-open fault) is used to model such open defects, and two pattern tests are required to detect the fault. The first pattern initializes the faulty gate output, while the second pattern activates the fault and propagates the fault effect to an observable output. It has been assumed that since delay caused by such open faults is generally very large, the test patterns are only sequence dependent instead of also being timing dependent as is the case in transition delay fault (TDF) testing. Thus these opens can be detected by either stuck-at tests (for the easy to initialize faults) or two-pattern TDF tests. However, due to the significant leakage current observed in current advanced CMOS technology, stuck-at (DC) tests are no long effective in detecting many open defects which, in effect, behave like delay faults. In addition, recent studies have shown that high quality TDF tests do not detect many open faults due to the fact that the detecting conditions for TDFs cannot always guarantee the explicit targeting of TSOFs. Furthermore, a large number of TSOFs are still undetected by even targeted TSOFs in the LOC scan test mode; many of these can actually cause circuit malfunction. This is because common hazards during normal circuit transitions may activate TSOFs that do not appear to be activated from a functional state in timing unware analysis. In this work we propose a circuit transformation scheme to use existing ATPG to generate targeted tests for TSOFs in primitive and complex gates in a scan test environment, using both LOC and LOS test modes. To allow the LOS tests to be applied at the highest achievable speed when an at-speed scan enable is not supported, we present a scan enable timing evaluation methodology. A key contribution of this work is the development of hazard initialized tests for targeting TSOFs undetected by traditional LOC and LOS timing unware tests but can be activated by hazards. To improve test efficiency we also present a new DFT scheme with multiple independent scan enable control signals that allows mixed LOC and LOS tests to be applied to the CUTs to boost TSOF coverage beyond that that achievable from traditional LOC and LOS tests. Finally, in order to understand the yield loss due to systematic process and layout effects early in the manufacturing process, and assist with yield ramp, it is also important to locate the physical open failures inside the defective chip. The few studies that have addressed TSOF diagnosis so far have been primarily based on stuck-at tests or have employed stuck-at diagnosis tools. We present an improved TSOF diagnosis scheme employing two-pattern scan test that generates diagnostic tests for the all non-redundant TSOFs, including those undetected by stuck-at and TDF tests.en_US
dc.rightsEMBARGO_NOT_AUBURNen_US
dc.subjectElectrical Engineeringen_US
dc.titleTesting and Diagnosis of CMOS Open Defects in the Presence of Common Hazardsen_US
dc.typeDissertationen_US
dc.embargo.lengthMONTHS_WITHHELD:13en_US
dc.embargo.statusEMBARGOEDen_US
dc.embargo.enddate2016-07-31en_US
dc.contributor.committeeAgrawal, Vishwanien_US
dc.contributor.committeeNelson, Victoren_US
dc.contributor.committeeDai, Faen_US


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