Reliability and Modeling of 32nm SOI Transistors at Cryogenic Temperatures

Abstract

With conventional transistor scaling rules and performance trends coming to an end, new methods are being explored to continue the advancements of electronic devices. One such method is to operate the devices in cryogenic environments. A few concerns for cryo genic electronics are the device reliability and lack of cryogenic models. Integrated circuits fabricated using a 32 nm SOI technology containing MOSFET transistors are stressed and measured at room temperature and in liquid helium to determine how the characteristics of the transistors change as a function of temperature. Various high voltage bias are applied to the gate and drain of an nFET transistor to induce hot carrier effects in the gate oxide of the transistor. Different gate widths are being tested to understand the geometrical impacts on reliability. Using the transistor characteristics gathered from the different widths, scalable cryogenic SPICE models are developed.