Design and Simulation of Cryogenic Test Circuits

Abstract

New technologies are being introduced in anticipation of the end of Moore’s Law, such as quantum computing, in hopes that the speed gains from the different topologies will offset the increase in size of the devices. Fast digital logic families have also evolved, including reciprocal quantum logic, rapid single flux quantum logic, and several more, that operate using quantum effects while being founded on conventional digital logic. One main issue with these logic families, and quantum computing for that matter, is their reliance on cryogenic temperatures to operate. Though these logic families are viable technologies, they are not very efficient in terms of data throughput unless the bandwidth in and out of the cryogenic dewar is sufficiently high. This requires high speed level shifters and generally protocol translators, such as serializer/deserializers, in order to interface to current generation digital logic. Thus, there is much interest in the operation of currently available low power CMOS circuits at cryogenic and near-cryogenic temperatures. Test circuits in a variety of current generation CMOS processes have been designed and simulated, in hopes to show functioning circuits at cryogenic temperatures. Test circuits range from simple ring oscillators to static and dynamic memory structures to more complicated synthesized ALU-like circuits, such as a multiply-accumulate unit.