Post Ion-Implantation Surface Palnarization Process for 4H-SiC Wafers Using Carbon Encapsulation Technique

Abstract

Metal oxide semiconductor (MOS) technology forms the core of the semiconductor power devices. The electronic properties of wide band gap semiconductor materials like 4H-SiC has attracted considerable interest for fabrication of high power and high frequency devices. The Si-face terminated 4H-SiC is extensively used in fabrication of these devices. However, the rate of oxidation of Si-face 4H-SiC is lower compared to C-face 4H-SiC materials. This high rate of oxidation of C-face 4H-SiC can be used as an advantage in decreasing the overall fabrication time. Extensive gate oxide reliability Si terminated 4H-SiC are available in literature. However, the gate oxide reliability studies on C-face 4H-SiC are still in early stages. In this work, the reliability of the thermally grown gate oxide on C-face 4H-SiC is studied. Oxides grown on epitaxial material showed superior oxide reliability compared to oxides grown on aluminum (Al) and nitrogen (N) doped substrates. This is attributed to the damage of the surface caused by high energy ions used for implantation. In addition, the surface is further roughened during the high temperature activation annealing (1450 0C - 1650 0C) which is performed to make the impurity atoms electrically active. Atomic force microscopy (AFM) analysis was performed at Vanderbilt University on the surfaces of C-face 4H-SiC to study the damage caused by implantation and post-implant annealing processes. The roughness values obtained by AFM were correlated with the oxide reliability measurements. Current-voltage (I-V) measurements were performed to calculate the dielectric breakdown field strength values for Al and N implanted samples with varying concentrations of 8 x 1015 to 6 x 1019 atoms/cm3. These concentrations correspond to the source/drain region implants for p- and n- channel MOSFETs. AFM results indicate that the surface of the substrate roughens with increase in implant concentration. Ion channeling experiments on the surface of C-face 4H-SiC subjected to high temperature implantation and activation annealing substrates showed a deviation from the stoichiometric SiC to a carbon rich compound. This non-stoichiometric compound is detrimental for the performance of the gate oxide at high electric fields. In this thesis work, a protective carbon (graphitic) cap was used on the C-face 4H-SiC substrates to protect the surface from annealing damage. The AFM and IV results of the samples protected by the carbon cap revealed that the carbon encapsulation technique prevents the annealing damage, thereby increasing the reliability of the gate oxides.