|dc.description.abstract||Silicon carbide (SiC) is a compound material with a wide bandgap, high critical electric
field strength, high saturation drift velocity and high thermal conductivity, which makes it an
outstanding material among wide bandgap semiconductors for energy efficient power devices. In
conjunction with development of high-voltage SiC Schottky barrier Diodes (SBDs), vertical 4H
SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) has been commercially
available since 2010. However, one of the challenges for further development of 4H-SiC power
MOSFETs is to improve low channel mobility (µ) and poor oxide reliability attributed to the poor
quality SiO2/SiC interface with high density of interface traps (Dit). Nitric oxide (NO) annealing,
the standard post oxidation annealing approach for 4H-SiC MOS devices, has improved the
channel mobility of 4H-SiC MOSFETs from single digit to ~35 cm2/V·s by passivating interface
traps and results in the most reliable gate oxide compared to other interface engineering processes.
However, the passivation effect of NO annealing has been shown to be almost saturated due to the
competing between nitridation and oxidation reactions during high temperature annealing. Also, a
recent research proposed that high temperature NO annealing creates fast interface traps near the
4H-SiC conduction band edge, observed by C-𝜓s analysis. Theses fast traps can response to
frequencies higher than the typical high frequencies (100 kHz-1 MHz) used in hi-lo C-V
measurements and could be the main limiting factor for channel transport of 4H-SiC MOSFETs.
Thus, more effective approaches have to be developed beyond NO annealing to improve the
interface quality for next-generation SiC power MOSFETs.
In this work, shallow ion implantations in channel region with antimony (Sb) combined
with NO annealing have been investigated on channel transport of 4H-SiC MOSFETs. We found
that Sb doping in conjunction with NO annealing improves subthreshold slope (SS) as well as
channel mobility (~1.5x) of 4H-SiC MOSFETs compared with standard NO annealing. Threshold
voltage decreases with Sb doping due to the compensation of the p-type acceptors in the surface
region by Sb donors. Electrical characterization shows the primary effect of Sb is counter-doping
rather than trap passivation, which well explains why the improvement of channel mobility by Sb
doping is only obvious at low oxide fields, where Coulomb scattering is dominant.
We also employed borosilicate glass (BSG) formed by planar diffusion source annealing
and PECVD as the gate dielectric for 4H-SiC MOSFETs. We demonstrated an improved channel
mobility over a wide range of transverse electric fields with a peak value of 140 cm2/V·s (4x higher
than by NO annealing) by using BSG due to the effective reduction of fast interface trap density.
The correlation between B concentration at the interface of BSG/4H-SiC and electrical results
indicates that Dit decreases with increasing B concentration. In return, higher B concentration
results in higher channel mobility. We also observed a best μ-Vth trade-off by using the
combination of Sb implantation with BSG gate dielectric, which is a promising process for
utilizing on SiC power MOSFETs.
We have performed Hall effect measurements on 4H-SiC Hall bar MOSFETs to accurately
estimate free carrier concentration and carrier mobility in the inversion layer of 4H-SiC
MOSFETs. The results help better understand the mechanisms of different scattering effects on
carrier mobility with various interfacial chemical configurations by NO annealing, combination of
Sb doping and NO annealing, and BSG gate dielectric.||en_US