|dc.description.abstract||Flip chip technology offers numerous advantages over conventional packages by virtue of its electrical performance, greater input/output (I/O) flexibility and small size. This study focuses on two flip chip assembly process developments: large size, fine pitch lead-free capillary flow flip chip and wafer-applied bulk coated flip chip. The assembly process for a lid attached on the backside of the die was also investigated.
Large size, fine pitch lead-free flip chips are highly desirable for many industrial applications. In this research, the 20.5 millimeters square dies with pitches down to 6 mils were assembled on ceramic substrates. The solder bumps were 97.5Sn2.5Ag. Many process parameters, including reflow profile, flux dispensing and die cleaning, were optimized for the best assembly and reliability performance. The assemblies were subjected to air-to-air thermal cycle testing in the final stage. The assemblies exhibited greater than 2700 cycles of thermal fatigue characteristic life.
The wafer-applied bulk coated assembly process is a novel technique used in flip chip assemblies. A successful assembly process was implemented in this study. PCB dehydration prior to assembly, dispensing volume, reflow profile and placement parameters have been examined. The optimized assembly process is presented. Good solder wetting and void free underfill were achieved. Liquid-to-liquid thermal shock reliability tests were performed. The results of failure analysis also provided valuable information for future process and material development.
Flip chips with high thermal conductivity lids are currently being used in a flip chip package designed for high power applications due to its enhanced ability to dissipate heat. Here, attaching the lid to the backside of the die was investigated. Pure indium was used to solder attach the lid to the die. This study presents an overall lid assembly methodology, along with a report on the reliability testing of assembled parts.||en_US