|dc.description.abstract||Electronic products such as smart phone, tablet and personal computer have been populated in recent years, those devices may accidentally fall on the ground during operation. Therefore, understanding the reliability performance of those devices during impact is very necessary. Previously, JEDEC has published a drop test standard JESD22-B111 . This standard has standardized the test procedures and test conditions. Since board level drop test is a key qualification test for portable electronic devices, lots of researchers have been interested in both experiment and simulation. Since solder joint is one of the weakest link in electronic products, it is important to quantify the stress and strain amplitude of solder joint during drop and shock. However, there is lacking of method to measure the stress and strain of solder joint experimentally, because the size of solder ball is way small. Simulation is a way to approximate the stress and strain values of interconnects during deformation. In the literature, the Anand model have been widely used in thermal cycling simulation to characterize the mechanical properties of solder alloys. But it is barely used in drop and shock simulation. In this study, Input-G method with implicit solver was used to simulate the drop test. The Anand model was used to describe the constitutive behavior of lead free solder and compared with linear material. 3-D DIC was used to measure the dynamic full field response of PCB during drop test at different G-level. Further, experimental data was used to compare with simulation results at drop condition of 1500G and 0.5ms. Hysteresis loop and plastic work density were also extracted to evaluate damage to solder joint per impact.
In automotive applications, electronic system can get exposed to high temperature and vibration during their life cycles. Simultaneously high temperature and vibration can cause failure in electronic system. The reliability of electronic products can be improved through understanding of solder interconnects in the electronic system. Presently, the literature on mechanical behavior of lead-free alloys under simultaneous harsh environment of high-temperature vibration is sparse. Most of the prior research in this area of reliability of solder joints are focused on thermal cycling which includes low cycle fatigue failure modes. Relatively few researchers have studied the reliability in the simultaneous environment of thermal cycling and vibration. Previously, finite element method has been used to quantify deformation of solder joint during high temperature vibration.
In this study, it mainly focuses on effect of high temperature vibration on reliability of electronic packages. JEDEC dimension boards with 12 packages mounted are tested at its first natural frequency with different G-level and operating temperature. Digital image correlation method is used to measurement displacement and strain of the PCB during deformation. Finite element method is also used to simulate vibration event with Input-G method combining with Anand model. In order to increase the computational efficiency, a nonlinear sub-modeling technique is carried out to running simulation. Displacement and strain results were also extracted from simulation and verified with experimental results. Hysteresis loop and plastic work density have also been calculated from simulation. Weibull analysis was used to analyze characteristic life of electronic packages subjected high temperature vibration. Effect of temperature and vibration G-level on fatigue life of CABGA288 have been discussed. Based on the characteristic life, plastic work density and characteristic life of solder joint, life prediction models were carried out to predict the useful life of packages on board. Failure analysis was performed to find the failure mode.||en_US