Design of High Performance Radio-Frequency Phase-Locked Loops

Abstract

Phase-locked loop, or PLL, is widely used in different areas of electronic system such as wireless transceivers which use PLL to generate carrier signals. Nowadays, the requirement for ever increasing data rate puts more stringent requirement on wireless networks where PLL plays a critical role. The next generation PLL for 5G network is required to achieve lower phase noise, higher spurious free dynamic range, consume less power and operate over broader frequency range. In this dissertation, the classic type-II PLL structure will first be reviewed and studied. Some of the most critical PLL performance including noise, power and spur will be discussed. Next, three designs that I have been involved with during my PhD career will be presented in each of the following chapters. These PLL designs vary in architecture and emphasize on different aspects of performance. In my opinion, they represent some of the future trends in the architecture of the next generation PLLs. Each of these designs has adopted some novel ideas, aiming to improve some key performances compared to conventional architecture. Along with the discussion for theoretical analysis and working mechanism, the PLL design methodology and simulation setup for key performances will also be covered.