Test Methods and Reliability Modeling of Electronic Assemblies under High-G Shock

Abstract

Electronic systems and sub-assemblies undergo a myriad of stresses during operation in their lifetime. Electronics in consumer, aerospace and defense industries increasingly use commercial-off-the-shelf components in their prototyping phase for ease of availability and the cost. Portable consumer electronics may be subjected to shock and accidental drop during transportation and normal usage. In aerospace and missile applications the electronic assemblies may be subjected to high-acceleration stresses during transportation and normal operation. In consumer electronics, survivability in the mechanical drop is ascertained using the JEDEC JESD22-B111 test standard. Consumer products may be designed in several form factors which may likely differ from the test board size and part configuration. The existing configuration of the JESD22-B111 test standard does not impose identical strains during drop test on all the 15-components on the test board, requiring many boards to develop meaningful life distributions. Two new candidate designs intended to serve as replacements for the JEDEC JESD22-B111 test board have been analyzed. High speed imaging-based 3D DIC measurements have been used to capture transient strain histories along with finite element modeling at various board locations to quantify the symmetry of loading including transient mode shapes and interconnect strains at 1500G, 0.5ms shock and 2900G, 0.3ms shock. Correlation of performance in JEDEC drop test to actual product performance is often weak. In order to alleviate this limitation of the JEDEC test, a new test vehicle was designed in the form factor of the actual use application. Commercial-off-the-shelf (COTS) components more than often find applications in harsh environments. Sustainment of long-term systems requires the understanding of the survivability limits on newer fine pitch part architectures. Fine-pitch electronics at high-g loads requires the use of additional structural support such as underfills and potting encapsulations for better shock damping and improve survivability. The potting compounds may serve additional functions including the ability to sustain thermo-mechanical loads and the high humidity in transport, storage, and use environments. Failure of potted assemblies has been shown to be at the interface between the potting material and the printed circuit board. New packaging architectures, which often push the edge of the envelope in terms of miniaturization, cannot be compared with the state-of-art systems and lack decades of historical data to provide robust proof of their survivability. Tools and techniques are needed to determine the failure envelopes for new component technologies for operation under high acceleration loads in current and next-generation military systems. Component’s survivability in a product is influenced by many factors including board construction, the board size, board thickness, and component design rules. Interfacial delamination at the solder mask of potted electronics was shown as a major failure mode during mechanical drop/shock loading. Characterization of interfacial fracture toughness facilitates the use of computational tools to predict the onset of damage in potted electronics. The fracture properties and interfacial crack delamination of the PCB/epoxy interface were determined using three-point bend specimens with a pre-crack at the interface. The effect of cure temperature on the interface fracture toughness of potted assemblies was quantified. The fatigue life of the potted electronic sub-assemblies under cyclic bending loading was characterized along with extracting interface parameters for cohesive zone modeling. A damage modeling framework using cohesive zone modeling was developed to predict the onset of interfacial damage in potted test assemblies subjected to high-G shock loads up to 25,000G.