Die Stress Characterization and Interface Delamination Study in Flip Chip on Laminate Assemblies

Abstract

Thermo-mechanical reliability of flip chip on laminate packaging is a major concern when the assemblies are exposed to harsh operating environments such as space or automotive underhood applications. In this study, structural and thermal reliability of flip chip packages have been investigated during the assembly process and accelerated life testing using piezoresistive stress sensing test chips. Both 5 x 5 mm (FC200) and 10 x 10 mm (FC400) test chips fabricated on (111) silicon were utilized to characterize the complete die stress state on the device side of the chip in flip chip on laminate assemblies. The FC200 chip includes 11 eight-element sensor rosettes, a diode for temperature measurement, an eight-bit fuse style chip ID, and contains 200 ?m (8 mil) pitch perimeter solder bumps. The FC400 chip includes 19 stress sensor rosettes, 2 diodes for temperature measurement, a 10-bit fuse style chip ID, an embedded full coverage heater for heat transfer or power cycling experiments, and also contains 200 ?m pitch perimeter solder bumps. This flip chip study is divided into four parts. In the first part of this work, transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. It is well known that underfill has significant impact on flip chip package reliability. To investigate the effects of underfill on thermo-mechanical behavior of flip chip packages, three different underfill materials were used in this study. A total of 75 flip chip test boards (1 die size x 3 underfills x 25 samples per combination) were assembled at the CAVE SMT Line at Auburn University. In each assembly, the three-dimensional die surface stresses have been recorded during underfill cure, and after underfill cure (room temperature). In the second part of this work, the silicon die stresses occurring in flip chip assemblies have been characterized and modeled at extremely low temperatures. Stress measurements have been made down to -180 oC using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solder and underfill encapsulant from -180 to 150 oC to aid in this modeling effort. In the third part of this work, the stress variations occurring during thermal cycling from -40 to +125 oC have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. The stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation have been identified. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most