A Practical Quaternary FPGA Architecture Using Floating Gate Memories
Metadata Field | Value | Language |
---|---|---|
dc.contributor.advisor | Millican, Spencer | |
dc.contributor.author | Fadamiro, Ayokunle | |
dc.date.accessioned | 2020-05-11T18:58:23Z | |
dc.date.available | 2020-05-11T18:58:23Z | |
dc.date.issued | 2020-05-11 | |
dc.identifier.uri | http://hdl.handle.net/10415/7182 | |
dc.description.abstract | A new quaternary FPGA (QFPGA) architecture based on floating-gate memory elements is presented and analyzed. While technology scaling has delivered substantial FPGAperformance, consumer demands grow beyond what binary circuits can deliver. FPGAs implementing multi-valued logic (MVL) have been explored, but previously proposed architectures rely on non-standard fabrication techniques and optimistic performance analysis. Results show the proposed QFPGA implementation based on floating-gate memories has a competitive delay and power performance compared to equivalent binary implementations and previous QFPGA architectures from literature when simulated in FinFET technology. | en_US |
dc.subject | Electrical and Computer Engineering | en_US |
dc.title | A Practical Quaternary FPGA Architecture Using Floating Gate Memories | en_US |
dc.type | Master's Thesis | en_US |
dc.embargo.status | NOT_EMBARGOED | en_US |
dc.contributor.committee | Harris, Christopher | |
dc.contributor.committee | Adit, Singh |