Process Development of Double Bump Flip Chip with Enhanced Reliability and Finite Element Analysis

Abstract

Flip chip technology has drawn tremendous attention in electronic packaging in recent years due to the advantages it offers, such as better electrical performance, high I/O density and smaller size. However, as package sizes become smaller, with finer pitch and higher density, the standoff height of the solder joints becomes lower, which intensifies the effect of the coefficient of thermal expansion (CTE) mismatch between the die and the printed circuit board (PCB). Based on the Coffin-Manson relationship, higher standoff height provides a smaller shear strain in the solder joint and, therefore, a longer fatigue life. In this study, an area array flip chip with a double bump solder joint structure was developed to improve the reliability of the package by increasing the standoff height. The new double bump flip chip on board package consisted of the original solder bumps protected by a wafer applied, low CTE underfill and a second layer solder bumps surrounded by no-flow fluxing underfill. This combination benefited from the fluxing underfill’s advantage of faster throughput during assembly without sacrificing the reliability by having a low CTE underfill layer near the silicon die. The bump structure and package geometry were optimized using both simulation and experimental data. Surface Evolver software was used to predict both the solder bump geometry and the standoff height of the solder joint after double bump formation and assembly on board. The computational aspects of solder joint prediction were considered, including the surface tension and gravitational effects. The impact of the second layer solder paste volume on the resulting double bump system was investigated and the results served as a guideline for stencil selection. The restoring force which provides self-centering was calculated for the different cases. The modeling results showed good agreement with experimentally measured results. A three-dimensional nonlinear finite element analysis was also performed to further explore the solder joint fatigue in a flip chip package. The distributions of stress, strain and volumetric averaged accumulated plastic work in the package and their changes during thermal cycling were studied. Solder joint fatigue life was predicted using several different methodologies. The simulation results for a double bump flip chip model were compared to those of a regular single bump flip chip model and showed that the double bump flip chip experienced lower stress, smaller strain range during thermal cycling and lower accumulative plastic work per thermal cycle. This led to a fatigue life enhancement of about 40% compared with a single bump flip chip. These simulation results were validated experimentally with air-to-air thermal shock reliability tests.