Design of Direct Digital Frequency Synthesizer for Wireless Applications
Type of DegreeThesis
Electrical and Computer Engineering
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Direct Digital Synthesis can be practically defined as a means of generating highly accurate and harmonically pure digital representations of signals. High speed DDS presents an attractive alternative to use of Phase locked loop approach in the design of high bandwidth frequency synthesizers because of its features like sub-hertz frequency resolution, fast settling time, continuous phase switching response and low phase noise. Although the principle of the DDS has been known for many years, the DDS did not play a dominant role until recent years. Earlier DDSs were limited to produce narrow bands of closely spaced frequencies, due to limitations of digital logic and D/A converter technologies. Recent advances in integrated circuit technologies have brought about remarkable progress in this area. By programming the DDS, adaptive channel bandwidths modulation formats, frequency hopping, and data rates are easily achieved. This is an important step towards applications like software radio which can be used in various systems. The DDS could be applied in the modulator or demodulator, in the communication systems. The applications of DDS are restricted to the modulator in the base station. One of the important factors determining the spectral purity of DDS is the resolution of the values stored in the sine look up table (ROM). Increasing the size of the ROM for better spectral purity is not a good approach because of the higher power consumption, lower speed and increased cost of a larger ROM. The first part of this thesis discusses the design and implementation of phase accumulator in the high speed ROM less DDS with sine-weighted DAC. The basic logic blocks are implemented in SiGe technology. The second part of the thesis proposes a novel DDS architecture with a compressed ROM without degradation of quantization noise. The ROM compression algorithm proposed achieved a better compression ratio of 94.3:1 with little increase in hardware when compared to many popular compression algorithms, giving a worst case spur of -90.3 dBc.