Alternative Techniques for Built-In Self-Test of Field Programmable Gate Arrays

Abstract

In the Built-In Self-Test method of testing the logic and interconnect resources of the Field Programmable Gate Arrays (FPGAs), configuration time and time to retrieve of the test results dominate the duration of the test. The techniques presented in this thesis offer reduction in the configuration time and result retrieval time for the Bulit-In Self-Test using partial reconfiguration and partial configuration memory readback. Though the work has been done tarkgeting Xilinx Virtex-I and Spartan-II FPGAs, the method is general enough to be applied on any FPGA featuring Partial Run Time Reconfiguration (PRTR). We also evaluate the Computer Aided Design (CAD) tools that are mainly used for partial reconfiguration, for their usefulness in generatin test configurations for the programmmable interconnect and logic resources of an FPGA using the Built-In Self-Test method.