Novel Test Point Insertion Applications in LBIST

Abstract

Pseudo-random stimulus for digital test is an established industry practice due to its simplicity and significant fault coverage. However, when applied to modern circuits, pseudo-random stimulus can fail to excite and observe random pattern resistant (RPR) faults. These faults are common when logic circuitry becomes more complex, which naturally occurs with technology scaling. Techniques that attempt to detect RPR faults using logic built-in self-test (LBIST), including (1) modifying the pattern generator to create less “random” stimulus or (2) modifying circuits to make RPR faults more easily tested with random stimulus, known as test point (TP) insertion (TPI), is frequently used in industry due to its ability to be implemented on post-synthesis circuit netlists with minimal effort from circuit designers. TPI is adding extra hardware to circuit, an internal signal modified using a test mode primary input, each TP carries an overhead of a test primary input or more logic gates. Optimal TPI is known to be an NP-hard problem, thus current TPI methods use heuristics to overcome computational barriers. Artificial neural networks (ANNs) are computing paradigms that present opportunities to increase solution quality and overcome computational barriers imposed by TPI algorithms. This dissertation studies ANN-based TPI algorithms. The methods include collecting training data, training ANNs, and analyzing ANNs to evaluate test points (TPs). Experiments compare ANN-based TPI methods against equivalent heuristic algorithms in terms of circuit testability and computation time. Experimental results show ANN-based TPI can achieve high fault coverage with less execution time. Another concern for design-for-test (DFT) engineers is high test power since high-power tests can cause false failures and circuits become less reliable when large and instantaneous power dissipation causes overheating. The peak power of a test vector, if it exceeds the functional specification, can cause failure due to signal integrity problem. Higher than the specified average power consumed by test vectors would cause overheating and would force the LBIST to be run at reduced frequency test clock, thereby increasing the test time. Thus, techniques must reduce test power while keeping fault coverage acceptable. Control TPs can reduce switching activity and keep lines stable, thus decrease power consumption during test. However, control TPs may also cause fault coverage to decrease, thus some strategies must be used to balance power and fault coverage. This dissertation proposes power-targeting TPI. The method uses multi-phase strategies in power-targeting TPI to minimize the negative impacts on fault coverage. Multi-phase strategies divided one TPI process into multiple parts, and TPs will not always active during the test, instead, certain TPs will be active in certain part. Experiments compare different numbers of TPI phases and find the best number of TPI phases, and experimental results show power-targeting TPI can reduce test power while keeping fault coverage high.