Damage Prediction of Lead Free Ball Grid Array Packages Under Shock and Drop Environment

Abstract

The fatigue and damage of solder joints and also the potential for interface failure within BGA packages are caused by thermal cycling. In case of portable electronic products, fatigue is caused by repetitive drop and shock during transportation, or vibrations experienced in land-vehicles, air-planes, ships etc. The solder joint failure can then be attributed to the structural dynamics of the product. Therefore there is a need to develop predictive techniques for electronic failure mechanisms in shock and drop-impact. Drop survivability methodologies are developed using JEDEC drop testing methods. Deformation kinematics of printed circuit board assembly using high-speed imaging at 150,000 fps has been studied. Explicit finite element models are developed for fine-pitch BGAs using smeared property approach and validated with experimental results. Damage proxies for failure mechanisms at the copper-to-solder, solder-to-printed circuit board and copper-to-package substrate have been developed. Relative damage index based on transient strain history has been developed to show the damage progression w.r.t. number of drops to failure are investigated using damage superposition (Miner’s Rule). Various packages are studied such as plastic ball-grid arrays, flex ball-grid arrays for both 62Sn36Pb2Ag and 95.5Sn4.0Ag0.5Cu solder alloy compositions. Effects of thermal cycling from -40 degC to 125 degC, isothermal aging at 125 degC has been studied for life prediction of the packages. Structural dynamics of the printed circuit board has been studied using experimental modal testing techniques (laser vibrometers). 3-D Digital Image Correlation technique have been explored using ultra-high speed camera to study full-field strain and deformation of PCB populated with packages in shock/vibration testing. Failure modes and mechanisms have been studied using Scanning Electron Microscopy (SEM). Statistical Pattern Recognition (SPR) technique has been used to evaluate reliability degradation of electronic assemblies. It is observed that damage accumulated varies with surface finish of printed circuit board (ImAg, ImSn, and ENIG), drop height, solder joint composition, environment conditions and orientation.