Power and Performance Optimization of Static CMOS Circuits with Process Variation
Type of DegreeDissertation
Electrical and Computer Engineering
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With the continuing trend of technology scaling, leakage power has become a main contributor to power consumption. Dual threshold (dual-Vth) assignment has emerged as an efficient technique for decreasing leakage power. In this work, a mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS (Complementary Metal Oxide Semiconductor) circuit for any specified input-to-output critical path delay. Using dual-threshold devices, the number of high-threshold devices is maximized and a minimum number of delay elements is inserted to reduce the differential path delays below the inertial delays of the incident gates. The key features of the method are that the constraint set size for the MILP model is linear in the circuit size and a power-performance tradeoff is allowed. Experimental results show 96%, 28% and 64% reductions of leakage power, dynamic power and total power, respectively, for the benchmark circuit C7552 implemented in BPTM 70nm CMOS technology. Due to the exponential relation between subthreshold current and process parameters, such as the effective gate length, oxide thickness and doping concentration, process variations can severely affect both power and timing yields of the designs obtained by the MILP formulation. We propose a statistical mixed integer linear programming method for dual-Vth design that minimizes the leakage power and circuit delay in a statistical sense such that the impact of process variation on the respective yields is minimized. Experimental results show that 30% more leakage power reduction can be achieved by using a statistical approach when compared with the deterministic approach that has to consider the worst case in the presence of process variations. Compared to subthreshold leakage, dynamic power is less sensitive to the process variation due to its linear dependency on the process parameters. However, the deterministic techniques using path balancing to eliminate glitches, becomes ineffective when process variation is considered. This is because the perfect hazard filtering conditions can easily be destroyed even by a small variation in some process parameters. We present a statistical MILP formulation to achieve a process-variation-resistant glitch-free circuit. Experimental results on an example circuit prove the effectiveness of this method.