Built-In Self Test for Regular Structure Embedded Cores in System-on-Chip

Abstract

Miniaturization and integration of different cores onto a single chip are increasing the complexity of VLSI chips. To ensure that these chips operate as desired, they have to be tested at various phases of their development. Built-In Self-Test (BIST) is one technique which allows testing of VLSI chips from wafer-level to system-level. The basic idea of BIST is to build test circuitry inside the chip so that it tests itself along with the BIST circuitry. The idea of current research is to develop BIST configurations for testing memory cores and other regular structure cores in Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs). FPGA-independent BIST approach for testing memory cores and other regular structure cores in FPGAs is described in this thesis. BIST configurations were developed to test memory cores in Atmel and Xilinx FPGAs using this approach. Another approach which takes advantage of some of the architectural capabilities of Atmel SoCs to reduce test time is also described in this thesis.