This Is AuburnElectronic Theses and Dissertations

Injection Locked Frequency Multiplier and Divider for Millimeter-Wave Frequency Synthesis




Zhang, Yucai

Type of Degree

PhD Dissertation


Electrical and Computer Engineering

Restriction Status


Restriction Type


Date Available



The perpetual need for faster data rates continues to drive advancements in wired and wireless communication, pushing them toward higher operating frequencies. The upcoming 5G network demands mobile transceivers that can function across an extensive frequency spectrum, spanning from sub-6GHz to millimeter-wave frequencies. This presents fresh, significant challenges in designing integrated frequency synthesis circuits that achieve both low jitter and low power consumption. This dissertation highlights the author’s research endeavors encompassing three key areas: (1) An injection-locked mm-wave frequency multiplier equipped with a low-power auxiliary frequency tracking loop for robust locking. (2) Injection-locked frequency dividers offering wide-range integer and fractional division ratios. (3) The utilization of these components in a 40GHz mm-wave frequency synthesizer to achieve low noise and low power consumption. The frequency multiplier employs a 40GHz injection-locked oscillator (ILO) for 4x frequency multiplication. It incorporates a low-power digital frequency tracking loop (FTL) to detect actual frequency errors, enabling a wide operating range for the ILO while employing a high-Q tank for reduced power consumption. The frequency dividers leverage injection-locked dynamic latches to achieve low-power integer and fractional multi-modulus at mm-wave bands. Programmable divide ratios are achieved by adjusting stage delays using variable PMOS load resistance and varactor capacitance. Circuit analysis shows that by incorporating proper phase delays, the fundamental frequency mixing provides integer frequency division, while the second harmonic mixing enables fractional frequency division. The prototype divider operates within an input frequency band of 27-44GHz, offering division ratios programmable as 4, 4.5, 5, 5.5, and 6. Implemented in a 45nm PDSOI CMOS technology, it consumes a maximum power of 2.4mW at a 0.94V supply voltage, occupying a compact core area of only 1368μm2. Both the frequency multiplier and divider contribute to a two-stage mm-wave frequency synthesizer. This two-stage approach allows for separate handling of low phase noise frequency synthesis via a slope-reshaped Reference Sampling Phase-Locked Loop in the first stage and mm-wave frequency multiplication in the second stage, optimizing overall power efficiency. Fabricated using a 45nm PDSOI CMOS technology, the prototype synthesizer achieves 251fs integrated jitter with a power consumption of 20.6mW at 35.84GHz, achieving a Figure of Merit (FoM) of -238.9dB, and occupying a mere 0.41mm2. These achievements have been published in IEEE Custom Integrated Circuits Conference and IEEE Journal of Solid-State Circuits. In a short period of time, the publications have received impactful citations in leading journals and conferences.