On-wafer RF Characterization and Modeling of Noise, Linearity and Reliability of Advanced RF FinFETs

Abstract

This work investigates the RF characterization and modeling of noise, linearity, and reliability of advanced RF FinFETs. 5-nm technology devices are used in linearity and noise modeling, and 14-nm technology devices are used for reliability and noise γ factor. The impact of non-conducting RF and DC stresses on IO devices in a 14/16-nm production FinFET technology is investigated experimentally. Degradation of transistor I − V and key RF characteristics are examined. At Vgs=0 V, the DC, and RF stress degradations show very different time exponents (n), making quasi-static approximation impossible. RF NC stress produces more long-term transistor performance degradation than its DC NC stress counterpart for the same maximum drain voltage. Despite RF stress, it has a smaller degradation at short stress times. All the RF stress degradation share a common n and exhibit a Vds,max dependence that can be modeled using Takeda’s equation. At Vgs=0.5 V, a significant die-to-die degradation variation is observed for near-threshold stress, which we attribute to subthreshold current variations. By modeling the die-to-die variation of the source current, we show that the RF stress degradation is reasonably quasi-static. The result supports channel current as the pri mary source of hot carriers, as is in conducting stress [1], despite the much lower Vgs. A simple method for a quick inspection of the impact of die-to-die variation is demonstrated. In both cases, the modeled Vds,max is found to be sufficient for our intended PAs. RF measurements of Cgs, Cgd, gm, and gds suggest that the damages are located near the drain end of the channel within the pinch-off region in saturation.

The two-tone intermodulation linearity characteristics are investigated using RF measurement, circuit simulation with BSIM-CMG, and power series IP3 analysis. For a given VDS, there are two IP3 peaks with respect to VGS. The VGS of the second IP3 peak corresponds to the VGS for which the Vdsat is equal to the VDS when the VGS is used for VDS sweep. Key BSIM-CMG model parameters required for simultaneous fitting of DC I-V, S-parameters, and intermodulation distortion are provided, in which parameters for the DIBL effect are most important for distortion. Power series is used in device linearity analysis, and power series calculated IP3 well agrees with measurement and simulation. Eliminating extra self-heating on IP3 coefficients and correcting derivatives from large parasitics are key steps to obtain accurate IP3 in the power series method. Detailed power series IP3 analysis shows that A, B, and C cancel out, causing a peak of IIP3 for sweeping VDS. The IP3 is strongly affected by load resistance RL. It is also observed that the load resistance, RL, significantly influences the IP3.