|dc.description.abstract||Embedded computer systems are widely used in modern life and their use is expanding. One of the typical constraints in embedded systems, particularly in standalone devices, is their low power capacity. One way to expand the lifetime of battery is to reduce its power consumption; because of the quadratic relationship between power consumption in CMOS circuits and CPU voltage, researchers now can achieve power reduction by scaling down its supply voltage by applying Dynamic Voltage Scaling (DVS). However, reducing supply voltage also slows down CPU speed since supply voltage has a proportional relationship with clock frequency of processor, namely, CPU speed. As a result, DVS succeeds at the cost of system performance. However, in a Real-Time embedded environment, especially in Hard Real-Time embedded Systems, timing constraint is a critical element that cannot be ignored. Therefore, it is difficult to balance the power savings and system throughput so that all tasks will still complete before their deadlines.
In this thesis, we focus on tasks scheduled by Rate Monotonic (RM) algorithm in a Hard Real-Time embedded environment. We derive an equation for scaling worst case execution time (WCET) of each task and expanding each WCET with different factors according to corresponding task computation time until slack times are fully occupied. Different from other approaches, we combine the power consumption equation with the constraint of Rate Monotonic schedulability test (RM test). From the result of this solution, we find the minimum power consumption, at which the RM task set can still pass the RM test and guarantee all tasks will meet deadlines. Our approach can be categorized as an off-line Intra-Task Dynamic Voltage Scaling (IntraDVS).||en_US