Built-In Self-Test of the Programmable Interconnect in Field Programmable Gate Arrays

Abstract

Testing programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) is difficult because of the large number of wire segments and switches that must be tested. The adoption of Built-In Self-Test (BIST) for programmable interconnect testing has proven to be an effective method for ensuring the fault-free status of the interconnect network for previous FPGA architectures. The BIST approaches used in previous FPGA interconnect testing relied on several assumptions to obtain adequate fault coverage within the device. With the advancement of technology and complexity of next generation FPGAs, the assumptions used in previous work can no longer be applied. New BIST approaches must be developed that alleviate these assumptions, yet still obtain high fault coverage. BIST approaches used in previous FPGA interconnect testing are modeled and simulated for gate-level stuck-at and bridging fault coverage. New BIST approaches are proposed and also modeled and simulated. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectiveness of these BIST approaches for testing programmable interconnect resources in FPGAs. A cross-couple parity approach that best suits the Xilinx Virtex-4 FPGA architecture is chosen and implemented for routing BIST of the global double lines in the interconnect network.