Browsing by Author "Agrawal, Vishwani D."

Now showing items 1-20 of 23

Built-In Self-test for Input/Output Cells in Field Programmable Gate Arrays

Vemula, Sudheer (2006-08-15)

Programmable Input/Output (I/O) cells are an integral part of any Field Programmable Gate Array (FPGA). The resources associated with the programmable I/O cells are increasing as newer architectures of FPGAs are being ...

Built-In Self-Test for Input/Output Tiles in Field Programmable Gate Arrays

Lerner, Lee (2008-05-15)

Very large scale integration (VLSI) circuits use input/output (I/O) cells to both send and receive signals from external resources. Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) with FPGA cores offer ...

Built-In Self-Test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfiguration

Dhingra, Sachin (2006-08-15)

Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement virtually any digital circuit design. Built-In Self-Test (BIST) is a testing approach that enables the device to test ...

Current Sensing Completion Detection for High Speed and Area Efficient Arithmetic

Gadamsetti, Balapradeep (2010-12-17)

Adders and multipliers are the most widely used computational units in integrated circuits. In many compact low power and high speed designs, more complex arithmetic operations such as multiplication are performed through ...

Delay Test Scan Flip-flop (DTSFF) Design and Its Applications for Scan Based Delay Testing

Xu, Gefu (2007-12-15)

Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test ...

Dictionary-Less Defect Diagnosis as Real or Surrogate Single Stuck-At Faults

Alagappan, Chidambaram (2013-04-05)

In this work, an algorithm to diagnose classic single stuck-at-faults and provide surrogate fault suspects for non-classical faults like multiple faults by analyzing failing circuits is proposed. The algorithm is based on ...

Energy Efficiency and Process Variation Tolerance of 45 nm Bulk and High-k CMOS Devices

Venkatasubramanian, Muralidharan (2011-04-18)

With transistor sizes being reduced to sub 45nm ranges, we have seen an improvement in speed, better performance, and deeper integration of digital circuits. However, there has been a corresponding increase in power ...

Energy Source Lifetime Optimization for a Digital System through Power Management

Kulkarni, Manish (2010-11-16)

This work analyzes a typical battery powered digital electronic system and we propose a system level voltage scaling method and a functional power management method called instruction slowdown for low power. In the first ...

Failure Evasion: Statistically Solving the NP Complete Problem of Testing Difficult-to-Detect Faults

Venkatasubramanian, Muralidharan (2016-12-08)

A circuit with n primary inputs (PIs) has N = 2n possible input vectors. A test vector to correctly detect a fault in that circuit must be among those 2n n-bit combinations. Clearly, this problem can be rephrased as a ...

Fault Detection and Diagnostic Test Set Minimization

Shukoor, Mohammed Ashfaq (2009-02-16)

The objective of the research reported in this thesis is to develop new test generation algorithms using mathematical optimization techniques. These algorithms minimize test vector sets of a combinational logic circuit for ...

A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management

Sheth, Khushbooben (2009-05-15)

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this truer than for portable, battery-operated applications, where power consumption has perhaps superseded speed ...

Hierarchical Fault Collapsing for Logic Circuits

Sandireddy, Raja-Kiran-Kumar (2005-05-15)

The process of grouping stuck-at faults into equivalence or dominance classes and then selecting one representative for each class is known as fault collapsing. There have been several techniques to collapse the faults ...

Independence Fault Collapsing and Concurrent Test Generation

Doshi, Alok (2006-05-15)

The objective of this work is to find suitable targets for Automatic Test Pattern Generation (ATPG) such that a minimal test set is obtained for a combinational circuit. Original concepts of independence fault collapsing ...

Low Temperature Modeling of I-V Characteristics and RF Small Signal Parameters of SiGe HBTs

Xu, Ziyan (2009-11-11)

SiGe HBT has been attached great attention recently to be used for space exploration due to its high-quality performance compared with conventional Si bipolar transistor over an extremely wide temperature range. The ...

Neuro-Fuzzy System with Increased Accuracy Suitable for Hardware Implementation

Govindasamy, Kannan (2009-05-15)

Fuzzy controllers are easy to design for complex control surfaces but produce rough control surfaces which might lead to unstable operation. On the other hand neural controllers are hard and complex to train but they produce ...

Power and Performance Optimization of Static CMOS Circuits with Process Variation

Lu, Yuanlin (2007-08-15)

With the continuing trend of technology scaling, leakage power has become a main contributor to power consumption. Dual threshold (dual-Vth) assignment has emerged as an efficient technique for decreasing leakage power. ...

Practically Realizing Random Access Scan

Mudlapur, Anand (2006-05-15)

The number of clock cycles in a serial scan (SS) test is often prohibitive as the number of flip-flops (FF) increases. Besides, scan-in and scan-out sequences result in unwanted circuit activity. This increases the test ...

Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits

Hu, Fei (2006-05-15)

Power dissipation is an increasingly critical issue in modern VLSI design and testing. Previously, linear programming (LP) based methods have been proposed for optimization of circuits for low power dissipation. However, ...

Reconvergent Fanout Analysis of Bounded Gate Delay Faults

Grimes, Hillary (2008-08-15)

To determine the quality that a set of gate delay tests provides for testing gate delay faults, gate delay fault simulation must determine the minimum size detectable for detected gate delay faults. The minimum size ...

Simulation Based Power Estimation For Digital CMOS Technologies

Alexander, Jins (2008-12-15)

The estimation of power in digital CMOS circuits has become a significant problem, especially for present day semiconductor technologies. Finding a balance between opposing factors of estimation accuracy and computation ...