Browsing by Author "Singh, Adit"

Now showing items 1-20 of 27

Alternative Timing in Digital Logic

Conover, George (2015-12-14)

For many decades using a system clock has been the go-to method of timing circuits. CPUs in particular have been at least partially defined by the speed of their clock. As technology moves forward, this is proving more and ...

Built-In Self Test for Regular Structure Embedded Cores in System-on-Chip

Garimella, Srinivas (2005-05-15)

Miniaturization and integration of different cores onto a single chip are increasing the complexity of VLSI chips. To ensure that these chips operate as desired, they have to be tested at various phases of their development. ...

Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip

Harris, Jonathan (2004-12-15)

Built-In Self-Test configurations for the logic and routing resources present in the Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis. These configurations completely test the Programmable ...

Built-In Self-Test of the Programmable Interconnect in Field Programmable Gate Arrays

Dixon, Bobby (2008-12-15)

Testing programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) is difficult because of the large number of wire segments and switches that must be tested. The adoption of Built-In Self-Test (BIST) ...

Current Sensing Completion Detection for High Speed and Area Efficient Arithmetic

Gadamsetti, Balapradeep (2010-12-17)

Adders and multipliers are the most widely used computational units in integrated circuits. In many compact low power and high speed designs, more complex arithmetic operations such as multiplication are performed through ...

DC Parametric Test and IDDQ Test Using Advantest T2000 ATE

Ding, Jialin (2015-07-24)

For purpose of improving quality of devices before shipping to customers, VLSI testing methods have been developed to detect defective devices effectively by using automatic test equipment (ATE). To test a chip properly, ...

Delay Test Scan Flip-flop (DTSFF) Design and Its Applications for Scan Based Delay Testing

Xu, Gefu (2007-12-15)

Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test ...

Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults

Zhang, Yu (2012-03-28)

In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. ...

Digital Testing with Multi-Valued Logic Signals

Li, Baohu (2015-04-27)

The integrated circuit scaling has been following the Moore’s Law since 1965 [59, 60, 61]. Within these decades, researchers made great effort to shrink the transistor feature size and maximize the integration level. ...

Exploiting Boundary Scan functions of FPGA on ATE

Zeng, Kunpeng (2015-07-21)

With the increase of integration density at chip level, the controllability and observability of defects become complicated, resulting in limited physical probe access to I/O pins. It is impractical to apply test stimulus ...

Exploiting Power-Up State of Latches as Hardware Security Primitives: PUF, TRNG and Recycled IC Detection

Wang, Wendong (2022-03-22)

Over the last two decades, hardware security has become more and more important and became a hot topic in both academia and industry. Threats seen on cyber-infrastructure and electronic devices are becoming more and more ...

A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management

Sheth, Khushbooben (2009-05-15)

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this truer than for portable, battery-operated applications, where power consumption has perhaps superseded speed ...

A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays

Uppu, Ravi Tej (2013-05-16)

The primary goal of this work is to ensure that optimum performance is achieved for a Multiplier Design, while reducing as much static power dissipation as possible or atleast equal to their slower counterparts. This design ...

Novel Approaches for Microelectronics Security and Test

Zhou, Ziqi (2021-08-05)

Due to the globalization in semiconductor industry, the cost of maintaining a foundry is enormous. Hence, most integrated circuit (IC) design houses have become fabless. Typically, a design house acquires multiple third ...

Novel Fault Injection Attacks on Logic Locking using ATPG

Jain, Ayush (2020-07-31)

The outsourcing of the design and manufacturing of integrated circuits (ICs) in the current horizontal semiconductor integration flow includes untrusted entities that have posed various security threats, such as overproduction ...

Novel Test Point Insertion Applications in LBIST

Sun, Yang (2021-11-15)

Pseudo-random stimulus for digital test is an established industry practice due to its simplicity and significant fault coverage. However, when applied to modern circuits, pseudo-random stimulus can fail to excite and ...

Output Hazard-Free Test Generation Methodology

Menon, Sreekumar (2009-03-25)

Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly ...

Path Delay Tuning for Performance Gain in the face of Random Manufacturing Variations

Mishra, Kautalya (2011-04-18)

Moore's laws predictions of transistor densities doubling every two years in an integrated circuit has held true for the past fifty years, and is predicted to hold true in the coming few years. But as technologies shrink ...

Practically Realizing Random Access Scan

Mudlapur, Anand (2006-05-15)

The number of clock cycles in a serial scan (SS) test is often prohibitive as the number of flip-flops (FF) increases. Besides, scan-in and scan-out sequences result in unwanted circuit activity. This increases the test ...

Pre-bond TSV Test Optimization and Stacking Yield Improvement for 3D ICs

Zhang, Bei (2014-12-10)

Through silicon via (TSV) based three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration,reduced delay and power dissipation, compact device ...