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Browsing by Author "Singh, Adit D."

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Better Than Worst Case Timing Design With Latch Buffers On Short Paths 

Uppu, Ravi Kanth (2013-11-08)
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its ...

An Efficient Transition Detector Exploiting Charge Sharing 

Wang, Yu (2014-12-09)
Transition detectors have been widely employed for online error and metastability detection, including in Better-Than-Worst-Case (BTWC) timing design of microprocessors that are designed to allow occasional timing errors. ...

Failure Evasion: Statistically Solving the NP Complete Problem of Testing Difficult-to-Detect Faults 

Venkatasubramanian, Muralidharan (2016-12-08)
A circuit with n primary inputs (PIs) has N = 2n possible input vectors. A test vector to correctly detect a fault in that circuit must be among those 2n n-bit combinations. Clearly, this problem can be rephrased as a ...

Finding Optimum Clock Frequencies for Aperiodic Test 

Gunasekar, Sindhu (2014-04-29)
With scale down in technology, size and complexity of integrated circuits increase. The scan method is the most popular technique of testing sequential circuits today. In this method, ip- ops functionally form one or ...

Reducing ATE Test Time by Voltage and Frequency Scaling 

Venkataramani, Praveen (2014-03-20)
During wafer sort, the fabricated chips are subjected to tests that verify if they meet the design specification. Test application time plays a critical role while verifying large volume of dice in a given period of time. ...