Built-In Self Test of Configurable Memory Resources in Field Programmable Gate Arrays

Abstract

Testing embedded memory resources in Field Programmable Gate Arrays (FPGAs) is difficult because the collective signal fan-in and fan-out is much greater than the available external I/O. A testing approach is needed that can test all of the memory resources in parallel without out being limited to external I/O. Built-in Self Test (BIST) is a testing method that incorporates test circuitry around the devices under test (DUT). The programmable nature of FPGAs allows the BIST circuitry to have no performance and size overhead because the BIST circuitry can be downloaded to the FPGA while the system is offline. Once offline, resources inside the FPGA can be tested and the results retrieved. If the FPGA is found to be fault-free then the system function can be downloaded again and brought back online.

BIST for embedded memory resources in Virtex 4 FPGAs is developed and test configurations are generated for all Virtex 4 devices. Twenty-five total BIST configurations are developed to test memories operating in RAM, FIFO, ECC, and cascade modes. To test each operating mode, a hardware design language (HDL) based test pattern generator (TPG) is developed and then incorporated into an algorithmically placed BIST template that contains two TPGs, DUTs, and output response analyzers (ORAs) to observe DUT outputs. Partial reconfiguration is used to reduce both configuration bitstream storage and test time. A total speed-up factor of 12 is observed when utilizing partial reconfiguration.