3D Device Simulation of SEU-Induced Charge Collection in 200 GHz SiGe HBTs
Type of DegreeThesis
Electrical and Computer Engineering
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This thesis presents three dimensional device simulations of SEU (single-event upset)-induced charge collection in 200 GHz SiGe HBTs. The device was constructed and simulated using Davinci. The charge collected by each terminal of the device is a strong function of the location of the ion strike. The sensitive regions of charge collection for each terminal are identified based on analysis of the device structure, the ion strike positions and the simulation results. For a strike between the deep trench edges, most of the electron and holes are collected by collector and substrate terminals, respectively. For a strike between the shallow trench edges surrounding the active emitter area, base terminal collects appreciable charges. The emitter terminal always collects negligible charges. A new junction passing / deep trench (DT) confinement model for angle strike dependence is supported by the simulations. Angled strike does NOT mean increased eˆective linear energy transfer (LET). Angled strike in DT isolated HBT in general v produces less charge collection. DT isolation ring limits the reach of charge collection available to the collector/substrate (C/S) junction. An ion that does not pass either collector-base or collector-substrate junctions produces little charge collection for lightly doped substrate. Then we propose new back junction approach to reduce charge collection in SiGe HBTs, and demonstrate its eˆectiveness in a 200 GHz SiGe HBT technology using 3-D device simulation. A wider n+ sinker around the deep trench perimeter helps by enhancing back junction charge collection, hence reducing charge collection at the sensitive collector node. A thinner p-type ""substrate"" layer also eˆectively decreases collector charge collection.