Power-Aware System-on-Chip Test Optimization through Frequency and Voltage Scaling

Abstract

A System-on-Chip (SoC) is a complete system that has been integrated onto a single chip. An SoC is often designed by embedding reusable blocks called cores. With shrinking device sizes, SoC cores are growing in number and complexity, which has led to high volumes of test data and resulted in long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of System-on-Chip (SoC) testing. Power dissipation during test mode is often much higher than that of functional mode and hence, test power management is also a major concern in SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Within these test schedules, the core tests may (as in the case of session-based test schedule) or may not (as in the case of sessionless test schedule) be grouped into test sessions. Traditional SoC test methods assume a constant test frequency and supply voltage (VDD) for the entire test schedule. However, test time and test power can be regulated by VDD and test clock frequency to optimize SoC test schedules for a given power budget.

The research presented in this dissertation focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be session wise (in the case of a session-based test schedule) or dynamic (in case of sessionless test schedule). SoC testing can be sped up by increasing the test clock rate. However, test clock is constrained by the rated power limit (power constraint) and the critical path delay (structure constraint) of the SoC cores. These constraints can be manipulated using VDD. Therefore, by scaling VDD and clock rate, an optimal test time and schedule can be obtained for an SoC.

For the session-based test scheduling, the optimization problem is mathematically formulated and solved through Integer Linear Program (ILP) based methods to provide optimal solutions. For SoCs with large number of cores, Integer Linear Programs are NP-hard and, in general, computationally expensive. To overcome this difficulty, a simulated annealing based heuristic method capable of providing near-optimal solutions is developed. Results show that the overall SoC test time can be considerably shortened by scaling the test clock and supply voltage. A similar heuristic method that is based on simulated annealing algorithm, is developed for the optimization of sessionless test schedules. The heuristic approach is capable of both preemptive (tests can be halted and resumed at will) and non-preemptive scheduling (tests cannot be interrupted at any time). Here also, the optimization results show a significant test time reduction over conventional reference test schedules where VDD and clock are fixed at given nominal values.