An 8-bit 80-MS/s SAR ADC with Proposed S/H and Control Logic

Abstract

In recent years, state-of-the-art Successive Approximation Register (SAR) ADCs have been operated at hundreds of MHz bandwidth or even GHz bandwidth by time interleaved for communication applications. This thesis proposes an 8-bit 80-Ms/s single-core SAR ADC implemented in 130nm CMOS. The differential input signal is sampled by the bootstrapped switch with cross-couple paths and dummy switches for linearity improvement. A capacitive DAC with constant common mode, set-and-down principle, and shrunk MSB capacitor is implemented for increasing speed and reducing mismatch. A two-way alternate comparator structure is proposed for speed improvement which eliminates the reset time, mux logic chooses 2 of the 3 comparators for interleaving while the offset calibration is operated in the idle comparator. A modified DAC switching logic is proposed to decrease the delay of the D flip flop. This design consumes 2mW from the 1.1V supply and occupies an area of 0.2952 mm2.