High Frequency Noise Modeling and Microscopic Noise Simulation for SiGe HBT and RF CMOS

Abstract

RF bipolar and CMOS are both important in RFIC applications. Modeling of noise provides critical information in the design of RF circuits. Unfortunately, available compact models for both RF bipolar and CMOS, are typically not applicable for the GHz frequency range. In this dissertation, a new technique of simulating the spatial distribution of microscopic noise contribution to the input noise current, voltage, and their correlation is presented, and applied to both RF SiGe HBT transistor and RF MOSFET transistor.

For RF SiGe HBT transistor, bipolar transistor noise modeling and noise physics are examined using microscopic noise simulation. Transistor terminal current and voltage noises resulting from velocity fluctuations of electrons and holes in the base, emitter, collector, and substrate are simulated using the new technique proposed, and compared with modeling results. Major physics noise sources in bipolar transistor are qualitatively identified. The relevant importance as well as model-simulation discrepancy is analyzed for each physical noise source.

Moreover, the RF noise physics and SiGe profile optimization for low noise are explored using microscopic noise simulation. A higher Ge gradient in a noise critical region near the EB junction, together with an unconventional Ge retrograding in the base to keep total Ge content below stability, when optimized, can lead to significant noise improvement without sacrificing peak cutoff frequency and without any significant high injection cutoff frequency rolloff degradation.

For RF MOSFET transistor, RF noise of 50 nm Leff CMOS is simulated using hydrodynamic noise simulation. Intrinsic noise sources for the Y- and H- noise representations are examined and models of intrinsic noise sources are proposed. The relations between the Y- and H- noise representations for MOSFETs are examined, and the importance of correlation for both representations is quantified. The H- noise representation has the inherent advantage of a more negligible correlation, which makes circuit design and simulation easier.

The extrinsic gate resistance is important as well as the intrinsic drain noise current for noise modeling of scaled MOSFET. Accurately extract the gate resistance becomes an important issue. The frequency and bias dependence of the eˆective gate resistance are explained by considering the eˆect of gate-to-body capacitance, gate to source/drain overlap capacitances, fringing capacitances, and Non-Quasi-Static (NQS) eˆect. A new method of separating the physical gate resistance and the NQS channel resistance is proposed.

Finally, drain current excess noise factors in CMOS transistors are examined as a function of channel length and bias. The technology scaling are discussed for diˆerent processes. Using standard linear noisy two-port theory, a simple derivation of noise parameters is presented. The results are compared with the well known Fukui’s empirical FET noise equations. Experimental data are used to evaluate the simple model equations. New figures-of-merit for minimum noise figure is proposed.