Low-Power, High-Performance Frequency Dividers for a Phase-Locked Loop
Type of DegreeMaster's Thesis
Electrical and Computer Engineering
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The world embraces the dawn of 5G implementation, and there is much work to be done. Companies, researchers, engineers, and many more posterities of people are pressing into high-frequency ranges, which presents a plethora of challenges. In the Radio Frequency Integrated Circuit Design (RFIC) field, dividers have received widespread interest. A frequency divider is a pivotal component of a Phase Lock Loop (PLL). The frequency divider is the feedback portion of the PLL, which receives the open-loop output. Thus, frequency dividers are the point of interest in this thesis. A frequency divider takes the input signal and divides it for reduced frequency output. Bandwidth is expensive; therefore, being able to reduce the frequency channels is of significant importance. The frequency divider reduces the frequency channels distance of a PLL, which is a significant factor when trying to return the open-loops output signal into the original reference frequency of the oscillator. Finally, a tunable divider would make this even more ideal. Being able to divide input frequencies by integer or fractional values would enable more applications for the finished PLL product.