High Speed Low Power Pipelined SAR ADC with Time Domain Based Fine Quantizer

Abstract

Due to the demanding requirements of speed, bandwidth, and power consumption of the latest-generation communication systems, designing analog integrated circuits serving the communication systems has become increasingly challenging. Analog-to-digital convertors (ADCs) are the essential part of the mixed-signal processing block and have encountered its bottleneck due to the extreme low power and high precision requirements, as well as the hardship brought by advanced CMOS technologies. In the recent ten years, the successive approximation register (SAR) analog to digital converter (ADC) architecture has gained the most popularity among other architectures for its good power efficiency. Nevertheless, the performance of the SAR ADCs is restricted when high resolution and speed are demanded. For instance, several hundred of Mega-Sample per second (MS/s) and higher than 10-bit resolution is hard to achieved efficiently with traditional SAR ADC approach. There are numbers of research and studies published each year to explore better solutions for combinations of high sample rate, high resolution, and low power consumption. The architectures of hybrid ADCs are proposed during the progressing research works. This dissertation studies fundamentals and advanced knowledges of SAR ADCs and presents various prototypes of power-efficient and PVT robust hybrid ADC which are based on pipelined successive approximation register (SAR) analog-to-digital convertor (ADC) architectures. In essence, prototypes of hybrid SAR ADC that utilizes time domain quantizer to improve the ADC performance are presented and discussed. In the presented work, a single-channel SAR ADC is adopted as the coarse quantizer, while a ring-configured time-to-digital-convertor (TDC) is utilized in the fine quantizer to improve the linearity and power efficiency. In addition, the ring-TDC also participates in the voltage-to-time conversion bridging two parts of the pipeline to ensure a PVT robust operation. The prototype ADC was fabricated in a 22-nm CMOS technology. When measured at 260MS/s, the ADC achieves 60.5-dB signal-to-noise and distortion ratio (SNDR) and 77-dB spurious-free dynamic range (SFDR) with a Nyquist input, while consuming 0.97-mW from a 0.8-V power supply. The calculated Walden and Schrier figure-of-merit (FoM) are 4.27-fJ/conversion-step and 171.8-dB, respectively. The ADC prototype illustrates a better solution for low power and high precision applications. The presented work is more feasible with advanced deep sub-micron technologies. It has proof that the combination of voltage domain and time domain quantization could be a smart choice for next-generation communication systems.