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dc.contributor.advisorLall, Pradeep
dc.contributor.advisorProrok, Bartonen_US
dc.contributor.advisorFlowers, Georgeen_US
dc.contributor.authorIyengar, Deeptien_US
dc.date.accessioned2008-09-09T22:33:22Z
dc.date.available2008-09-09T22:33:22Z
dc.date.issued2008-12-15en_US
dc.identifier.urihttp://hdl.handle.net/10415/1011
dc.description.abstractElectronics may be subjected to shock, vibration, and drop impact during shipping, handling, and normal usage. Measurement of transient dynamic deformation of the electronic assemblies during shock and vibration can yield significant insight in understanding the occurrence of failure modes and the development of failure envelopes. In this work, the transient dynamics of board assemblies in the form of relative displacement, drop angle, velocity, and acceleration were measured with high-speed imaging. In addition, high-speed data acquisition systems with discrete strain gages were used for measurements of transient strain at fixed locations. A new technique called digital image correlation (DIC) using ultra high-speed cameras for full-field measurement of transient strain was investigated. Various board assemblies subjected to shock at different drop orientations were examined. Accuracy of the high-speed optical vi measurements was compared with that from discrete strain gages. Explicit finite-element models were developed and correlated with experimental data. There is a fundamental need for the development of predictive techniques for electronic failure mechanisms in shock and drop-impact. Presently, one of the primary methodologies for assessment of shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 [JEDEC 2003] which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide array of boundary conditions beyond those targeted in the test method. Development of damage-equivalency methodologies will be invaluable in correlating standard test conditions to widely varying design-use conditions. In this work, the development of solder-joint stress based relative damage index was investigated to establish a method for damage equivalency. In practical applications, electronics are subjected not only to drop and shock but to a combination of loads. Thus, effect of overlapping stresses on the deformation behavior of solder interconnects was investigated. The effect of different package architectures and various surface finishes including ImAg, ImSn and ENIG on impact reliability was studied. Life prediction of new lead-free alloy-systems under shock and vibration is largely unexplored. An approach to model drop and shock survivability of electronic packaging is presented for six lead-free solder alloy systems including Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu-Bi, Sn0.3Ag0.7Cu-Bi-Ni, and 96.5Sn3.5Ag. The approach is scalable to a wide variety of electronic applications.en_US
dc.language.isoen_USen_US
dc.subjectMechanical Engineeringen_US
dc.titleInitialization and Progression of Damage in Lead Free Electronics under Drop Impacten_US
dc.typeThesisen_US
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US


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