Experimental Characterization and Compact Modeling of LDMOS Devices at Cryogenic Temperatures: Extensions to the PSPHV Model

Abstract

This work presents a comprehensive study of the electrical characteristics and compact modeling of Lateral Diffused MOS (LDMOS) transistors over a wide temperature range from approximately 21 K to 390 K. While LDMOS devices are widely used in high-voltage and RF applications, their behavior at cryogenic temperatures remains insufficiently understood, and existing compact models fail to fit the measured device characteristics accurately under such extreme operating conditions. To address this gap, systematic on-wafer cryogenic measurements were performed using a customized low-temperature probing setup. Special attention was devoted to mitigating common low-temperature measurement challenges—including mechanical vibration, system oscillation, and self-heating—which frequently obscure the intrinsic device behavior. The measured data reveal several unconventional cryogenic phenomena in LDMOS devices, including strong quasi-saturation, mobility-dominated conduction, nonlinear drift resistance behavior, subthreshold slope degradation driven by band-tail states, and notable threshold voltage saturation. These effects motivate the need for significant improvement beyond the standard PSPHV compact model. Building upon detailed physical analysis, a unified wide temperature range scaling framework is developed for PSPHV, incorporating updated mobility, threshold voltage, drift region, and transconductance temperature dependences. The resulting model enables accurate fitting of ID−VGS, gm−VGS, and ID−VDS characteristics across both low-field and high-field regimes over the full temperature range. To further evaluate geometry-dependent cryogenic behavior, narrow-width LDMOS devices were characterized and modeled. Dual-path channel conduction due to device edges, spatial VTH variation, and strong two-peak gm characteristics are analyzed within the edge-conduction structure of the PSPHV framework. For the wide device, a single set of unified scaling equations reproduces the measured characteristics across the full temperature range; for the narrow device, an isothermal extraction strategy with parameter clamping reproduces the data accurately at each temperature, and a fully unified cryogenic scaling for narrow-width effects is identified as future work. Overall, this dissertation provides a consistent, experimentally validated PSPHV modeling methodology for LDMOS devices from deep-cryogenic to high-temperature operation. The proposed unified temperature-scaling model significantly extends the temperature range over which PSPHV reproduces measured LDMOS characteristics, and offers a practical foundation for cryogenic IC design, compact-model development, and process optimization.