A Learned Cost Model for High-Fidelity Quantum Circuit Layout Optimization

Abstract

On Noisy Intermediate-Scale Quantum (NISQ) hardware, execution fidelity varies from one qubit assignment to another even when routing is absent, which makes layout selection a first-order determinant of circuit performance. Yet compilers choose it by connectivity rather than by noise. This thesis introduces FidelityRoute, a learned, fidelity-aware framework for qubit layout optimization built on a Graph Neural Network.

Trained on 27,278 unique circuit-layout samples, it predicts a normalized fidelity cost from pre-transpilation features alone and ranks candidate layouts inside an active search. On a circuit-disjoint test set it reaches R2 = 0.9976, but a circuit-mean baseline already reaches R2 = 0.9973, so that score reflects between-circuit scale rather than within-circuit layout discrimination; the ranking that matters gives a median Spearman of 0.615 across two qualifying circuits.

Across 30 benchmark circuits on a 127-qubit all-to-all backend, FidelityRoute beats a single-seed SABRE baseline on 19 of 30. That baseline is weak, however, since a random draw from the same pool beats it on 27 of 30. The advantage is strongest on small circuits with diverse pools, where selection is near-optimal, and does not extend to large circuits. A variance decomposition shows the binding constraint is candidate generation, not the model's representation. Fidelity is estimated analytically; hardware validation is the primary next step.